Sega 32X Manual Page 89
- Page / 102
- Table of contents
- BOOKMARKS
- Hardware Manual 1
- Doc. #MAR-32-R4-072294 1
- Terminology 4
- Contents 5
- 1. Introduction to 32X 7
- New Screen Offered 8
- New Sounds Offered 8
- High-Speed Microprocessor 8
- Development Language 8
- 2. Configuration 9
- Figure 2.1 32X Block Diagram 10
- MEGA Drive I/F Component 11
- 32X Cartridge Component 11
- SH2 Component 11
- SDRAM Component 12
- Frame Buffer Component 12
- VDP Component 12
- Color Palette Component 13
- PWM Component 13
- 3. Functions 14
- MEGA Drive Memory Map 15
- ROM Access when using the 32X 16
- Access to the 32X VDP 16
- SH2 Memory Map 17
- Figure 3.2 SH2 Memory Map 17
- Cache Area Access 18
- Cartridge ROM Access 18
- 32X VDP Access 18
- 1.5. Registers 19
- Using the 32X 21
- Interrupt issued for SH2 22
- Switches ROM Cartridge Bank 22
- (Acces : Word) 24
- (Access : Word) 24
- (Acces: Byte/Word) 25
- (Access : Byte/Word) 25
- (Access: Byte/Word) 26
- [SH2 side] 28
- (Access : Byte/Word) 28
- PWM Interrupt Clear Register 30
- (Access : Word) 32
- VDP Registers 36
- 1.6. VDP 39
- Figure 3.4 32X VDP Mapping 41
- Switching Frame Buffers 42
- Figure 3.7 Over Write Image 45
- Line Table Format 47
- Figure 3.8 Line Table Format 47
- Priority 48
- Figure 3.9 Priority 48
- Direct Color Mode 49
- Figure 3.10 Direct Color Mode 49
- Packed Pixel Mode 50
- Figure 3.11 Packed Pixel Mode 50
- Screen Shift Control 51
- Run Length Mode 52
- Figure 3.13 Run Length Mode 52
- FILL Function 53
- Before Fill 53
- After Fill 53
- Mega Drive Master Clock Cycle 54
- 68000 Clock Cycle 54
- SH2 Clock Cycle 54
- VDP Register Latch Timing 56
- 1.7. PWM 57
- Master and Slave 62
- Note 2 : See next page 63
- Figure 3.25 SH2 Address 64
- V: valid bit 64
- Purge (Cache Initialization) 66
- CPU Write 67
- Flow of Data 67
- Master-Slave Communication 68
- Communication Port 69
- CMD Interrupt 69
- 4. 32X Block Access 72
- SH2 Address Space 73
- Cache-through Access 74
- VDP Access Competition 74
- ROM Access Competition 74
- Competition with other CPUs 76
- Frame Buffer Access 76
- 32X Mode and Cartridge ROM 77
- Frame Buffer 77
- VDP Register 78
- System Register 78
- Boot ROM 78
- SDRAM Access Time 78
- 5. Other 79
- Initial Program 83
- Security 83
- 6. Annexes 88
- 1.16. Master Boot ROM 89
- 1.17. Initial program 95
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