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68K to SH DREQ Destination Address Register
(Acces : Word)
Sets the SH2 side (SDRAM) address. The DREQ circuit does not use this data. Thus,
when the destination address is known beforehand by SH2, or when SH2 doesnít need to
know, no settings are nedded.
68K to SH DREQ Length Register
(Acces : Word)
Sets the number of data items (unit : word) to be sent to SH2 side. The value to be set is in
4 word unites. Low order 2 bits write is ignored (00 fixed). Be sure to set this register for
CPU WRITE. At each transfer, this register is decremented and when it becomes 0, the
DREQ operation ends. Transfer is done 65 56 times when 0 is set. Read time reads the
actual count value.
FIFO Register
(Access : Word)
Data is written to this register when DREQ is used by CPU WRITE.
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