Sega 32X Manual download pdf (Page 4)

Terminology

RISC (Reduced Instruction Set Computer)

This computer architecture improves performance by simplifying instructions

specifications and has simplified hardware achieving a high efficiency pipeline (parallel

process of instructions within the computer).

SH2 (SH7095)

At the core of the RISC-type CPU in the Hitachi original microcomputer is a 32-bit

divider and cache memory.

Cache

The cache is comparatively small size high-speed memory placed between the large size

low-speed memory and the CPU. When data of the address to be accessed by the CPU is

stored in the cache memory, it is referred to as cache hits and because the data can be

accessed, the CPU can be operated at hight speeds. When address data to be accessed by

the CPU is not stored in the cache memory, it is referred to as a cache miss. The contents

of the cache memory is replaced by data in the main memory.

SDRAM (Synchronous Dynamic Random Access Memory)

The SDRAM differs from the typical DRAM data of a two line address is held internally

once. This is independantly synchronized to the clock and transfers continously separate

from the internal DRAM operation speed.

DSP (Digital Signal Processor)

Signal Processor containing a high-speed divider.

DMA (Direct Memory Access)

Transfers data directly between the memory and peripherals units (I/O) or between

memories without going trhough the CPU, usually achieved by the DMA controller

(DMAC)

FIFO (First-In First-Out)

Method of outputting in the same order as inputting in the input/ouput operation of a

buffer register or buffer memory.

Master / Slave

Refers to the prior order of user authorization of a bus to which more than one processoir

is connected. Master takes a normal bus authorization and slave obtains permission of the

master and takes bus athorization when slave bus access occurs.

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Sega 32X Manual Page 4